Zuken and Aldec have a brand new
collaborative product for complete FPGA design and verification.
This is called CADSTAR FPGA.
It combines
Aldec’s Active-HDL Lite verification tool and
Zuken’s
desktop PCB design suite, CADSTAR, allowing engineers to perform
mixed language simulation for vendor neutral FPGA design within the
CADSTAR environment.
![](CADSTAR_FPGA.jpg)
Vendor Independent Design Flow Manager
Design Entry Tools
Mixed VHDL/Verilog Simulation
Debugging
Logic Synthesis
Timing Simulation
Waveform Editor
![](CADSTA1.jpg)
and
more
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