CADSTAR FPGA

Zuken and Aldec have a brand new collaborative product for complete FPGA design and verification.

This is called CADSTAR FPGA.

It combines Aldecís Active-HDL Lite verification tool and Zukenís desktop PCB design suite, CADSTAR, allowing engineers to perform mixed language simulation for vendor neutral FPGA design within the CADSTAR environment.

Vendor Independent Design Flow Manager

Design Entry Tools

Mixed VHDL/Verilog Simulation

Debugging

Logic Synthesis

Timing Simulation

Waveform Editor

 

and more

 

 

 

 

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Website last updated December 10, 2009

Copyright Algozen Corporation 2009. All rights reserved