Zuken and Aldec have a brand new
collaborative product for complete FPGA design and verification.
This is called CADSTAR FPGA.
Aldecís Active-HDL Lite verification tool and
desktop PCB design suite, CADSTAR, allowing engineers to perform
mixed language simulation for vendor neutral FPGA design within the
Vendor Independent Design Flow Manager
Design Entry Tools
Mixed VHDL/Verilog Simulation