Zuken and Aldec have a brand new collaborative product for complete FPGA design and verification.

This is called CADSTAR FPGA.

It combines Aldec’s Active-HDL Lite verification tool and Zuken’s desktop PCB design suite, CADSTAR, allowing engineers to perform mixed language simulation for vendor neutral FPGA design within the CADSTAR environment.

Vendor Independent Design Flow Manager

Design Entry Tools

Mixed VHDL/Verilog Simulation

Debugging

Logic Synthesis

Timing Simulation

Waveform Editor

and more